As semiconductor technology progresses, high speed and highly integrated semiconductor devices are being developed, and thus a demand for pattern fitness has grown significantly.
Today, a process of forming a semiconductor device involves a device isolation forming process for establishing an active region in which an active device, such as a transistor, will be formed. Typically, the device isolation forming process used to form a device isolation film of a semiconductor device is a shallow trench isolation process (STI) that can widen an area of an active region due to a reduction of a design rule of a device, instead of a local oxidation of silicon (LOCOS).
The device isolation film formation by means of the STI process is a method of selectively etching a silicon wafer and forming a trench and then filling insulation materials in the trench.
Hereinafter, a process of forming a device isolation film of a semiconductor device according to the related art will be described with reference to FIG. 1 and FIG. 2.
Referring first to FIG. 1, a pad oxide film 2 and a pad nitride film 3 are formed on a semiconductor substrate 1.
Then, a trench 4 is formed on the semiconductor substrate 1 by forming a photoresist pattern (not shown) defining a device isolation region and then etching the pad nitride film 3, the pad oxide film 2, and the semiconductor substrate 1 using the photoresist pattern as an etch mask.
Referring to FIG. 2, an oxide film 5 is deposited on the semiconductor substrate 1 to fill the inside of the trench. The oxide film 5 is deposited at a thickness sufficient to form the oxide to the upper surface of the pad nitride film 3 while sufficiently filling the trench 4.
Then, the oxide film 5 is planarized by means of a chemical mechanical polishing (CMP) process. The CMP process is performed until the pad nitride film 3 is exposed and then is performed to remove the pad nitride film 3 and the pad oxide film 2, thereby completing a device isolation film.
However, as the design rule dimensions of the semiconductor device are reduced, the aspect ratio of the trench 4 is very large so that a void 6 may be generated in the trench when filling the trench 4 with the oxide film 5.
The void 6 is exposed when the oxide film 5 is planarized by means of the CMP so that in a subsequent gate forming process, a gate material may remain in the void 6. As a result of the void, the remaining gate material may be electrically connected to the gate. Such a defect may cause the characteristics of the semiconductor device to deteriorate and reduce reliability of the device.
In addition, the device isolation insulating film formed of the oxide film according to the related art process generates an electric field concentration effect which increases at corner portions thereof so that leakage current increases.